Method, apparatus and instructions for parallel data conversions

摘要

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

主权项

1. A system comprising:
a processor comprising a register file including a first packed data register and a second packed data register, a decoder to decode a first instruction, scheduling logic to allocate resources and queue operations corresponding to the first instruction for execution, and execution logic coupled to the decoder and the scheduling logic, wherein, responsive to the decoder decoding the first instruction, the execution logic is to convert a plurality of first packed signed data elements to a plurality of unsigned results, wherein the plurality of first packed signed data elements from the first packed data register is converted to the plurality of unsigned results, the unsigned results are saturated and stored in the second packed data register, and each of the first packed signed data elements has a first number of bits, each of the unsigned results has a second number of bits, and the second number of bits is one half the first number of bits; and a memory controller coupled to the processor, wherein the memory controller is integral with the processor.