发明名称 Silicon carbide trench MOSFET having reduced on-resistance, increased dielectric withstand voltage, and reduced threshold voltage
摘要 A semiconductor device (A1) includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), a trench (3), an insulating layer (5), a gate electrode (41), and an n-type semiconductor region (14). The p-type semiconductor layer (13) includes a channel region that is along the trench (3) and in contact with the second n-type semiconductor layer (12) and the n-type semiconductor region (14). The size of the channel region in the depth direction x is 0.1 to 0.5 μm. The channel region includes a high-concentration region where the peak impurity concentration is approximately 1×1018 cm−3. The semiconductor device A1 thus configured allows achieving desirable values of on-resistance, dielectric withstand voltage and threshold voltage.
申请公布号 US9024329(B2) 申请公布日期 2015.05.05
申请号 US201314049810 申请日期 2013.10.09
申请人 Rohm Co., Ltd. 发明人 Nakano Yuki
分类号 H01L29/15;H01L31/0312;H01L29/78;H01L29/10;H01L29/16;H01L29/66;H01L29/739;H01L29/06;H01L29/423;H01L29/45 主分类号 H01L29/15
代理机构 Hamre, Schumann, Mueller & Larson, P.C. 代理人 Hamre, Schumann, Mueller & Larson, P.C.
主权项 1. A semiconductor device comprising: a first semiconductor layer having a first conductivity type and made of silicon carbide; a second semiconductor layer made of silicon carbide, provided on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type; a trench penetrating through the second semiconductor layer to reach the first semiconductor layer; an insulating layer formed at a bottom and a side of the trench along an inner surface of the trench; a gate electrode insulated by the insulating layer from the first semiconductor layer and the second semiconductor layer, at least part of the gate electrode being formed inside the trench; and a semiconductor region made of silicon carbide, having the first conductivity type and formed around the trench on the second semiconductor layer; wherein the second semiconductor layer includes a region that is along the trench, the region of the second semiconductor layer that is along the trench includes a high-concentration region where impurity concentration is equal to or higher than 5×1017 cm−3, the high-concentration region is in a form of a layer that is in contact with the trench and that spreads in a direction perpendicular to a depth direction of the trench, and the high-concentration region has a peak impurity region in a medium portion of the second semiconductor layer along the trench.
地址 Kyoto JP