Nano-tube MOSFET technology and devices

摘要

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

主权项

1. A metal oxide semiconductor field effect transistor (MOSFET) comprising:
a semiconductor substrate having a plurality of trenches opened from a top surface; wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type; all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as one of said alternating conductivity types wherein said central gap-filler layer of a central conductivity type opposite the innermost conductivity type having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types and said central gap-filler layer constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches; and a body region encompassing source region surrounding a gate of the MOSFET disposed near a top surface of the pillar comprising the volume of the semiconductor substrate for conducting a current through the nano tubes to a drain region disposed on the bottom of the semiconductor substrate.