Method for self-aligned removal of a high-K gate dielectric above an STI region

摘要

By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

主权项

1. A method, comprising:
forming a gate layer stack above a semiconductor layer, said gate layer stack comprising a high-k dielectric layer and a metal-containing material formed on said high-k dielectric layer; forming a trench isolation structure in said gate layer stack, said trench isolation structure extending through said gate layer stack and into said semiconductor layer to isolate a first active region from a second active region; forming a first gate electrode of a first transistor above said first active region and a second gate electrode of a second transistor above said second active region; and forming a conductive material above said metal-containing material and directly overlying a top surface of said trench isolation structure, said conductive material forming an electrically conductive connection between said first gate electrode and said second gate electrode.