发明名称 Leadframe area array packaging technology
摘要 Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.
申请公布号 US9023690(B2) 申请公布日期 2015.05.05
申请号 US201213681302 申请日期 2012.11.19
申请人 United Test and Assembly Center 发明人 Dimaano, Jr. Antonio Bambalan;Suthiwongsunthorn Nathapong;Yang Yong Bo
分类号 H01L21/56;H01L23/31;H01L21/78;H01L21/50;H01L23/495;H01L21/48 主分类号 H01L21/56
代理机构 Haverstock & Owens, LLP 代理人 Haverstock & Owens, LLP
主权项 1. A method of fabricating a semiconductor package comprising: providing a carrier strip having top and bottom surfaces; applying a layer of polymer material on the top surface of the carrier strip; fabricating interconnects on a top surface of the layer of polymer material; assembling a package; decoupling the carrier strip from the package; forming a plurality of openings in the layer of polymer material; applying suitable material in the plurality of openings; and singulating the package from other packages, wherein the layer of polymer material is applied using an UV adhesive.
地址 Singapore SG