| 摘要 |
The present invention relates to a semiconductor memory device with a hierarchical bit line structure and a manufacturing method thereof. The semiconductor memory device with a hierarchical bit line structure according to the present invention includes: a plurality of word lines (WL) arranged in parallel in one direction, a plurality of local bit lines (LBL) which are orthogonal to the word lines and are arranged in parallel, and a plurality of cell transistors and cell capacitors which are connected between each local bit line and each word line. The present invention minimizes a coupling noise between global bit lines and minimizes a coupling noise between adjacent via contacts by equalizing the distance of the via contact. |
