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发明名称
Cu配线形成方法及记忆媒体
摘要
提供一种Cu配线形成方法,系可在凹部形成Cu配线时,抑制配线电阻之上升或工序之增加,且充分地确保埋入性,而可得到高电子迁移耐受性之Cu配线。;具有:在具有沟槽之晶圆整面形成阻隔膜的工序;藉由CVD来在阻隔膜上形成Ru膜之工序;藉由PVD来在Ru膜上形成Cu合金膜而将Cu合金膜埋入至沟槽之工序;在Cu合金膜上形成沉积层之工序;藉由CMP来研磨整面而形成Cu配线于沟槽之工序;以及在Cu配线上形成介电质盖层之工序。
申请公布号
TW201517212
申请公布日期
2015.05.01
申请号
TW103122015
申请日期
2014.06.26
申请人
东京威力科创股份有限公司 TOKYO ELECTRON LIMITED
发明人
横山敦 YOKOYAMA, OSAMU;韩千洙 HAN, CHEONSOO;佐久间隆 SAKUMA, TAKASHI;安室千晃 YASUMURO, CHIAKI;平泽达郎 HIRASAWA, TATSUO;石坂忠大 ISHIZAKA, TADAHIRO;铃木健二 SUZUKI, KENJI
分类号
H01L21/768(2006.01)
主分类号
H01L21/768(2006.01)
代理机构
代理人
林秋琴陈彦希
主权项
地址
日本 JP
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