| 摘要 |
一种三维堆叠半导体结构，包括：复数个堆叠形成于一基板上、至少一接触孔垂直形成于该些堆叠其中之一、一导电体形成于接触孔内、一电荷补捉层至少形成于该些堆叠之侧壁处。其中之一堆叠包括一多层柱体包括复数层绝缘层和复数层导电层交替堆叠而成，和一介电层形成于多层柱体上。接触孔系穿过对应堆叠的介电层、该些绝缘层和该些导电层。接触孔内的导电体连接对应堆叠的该些导电层。其中，导电体之上表面系高过于对应堆叠的多层柱体之上表面。; at least a contact hole formed vertically in one of the stacks; a conductor formed in the contact hole; and a charging trapping layer at least formed at sidewalls of the stacks.One of the stacks comprises a multi-layered pillar, including a plurality of insulating layers and a plurality of conductive layers arranged alternately, and a dielectric layer formed on the multi-layered pillar.The contact hole is formed vertically in one of the stacks, and the contact hole penetrates the dielectric layer, the insulating layers and the conductive layers of the corresponding stack.Also, a top surface of the conductor is higher than a top surface of the multi-layered pillar for the corresponding stack. |
