发明名称 |
DATA PROCESSING DEVICE AND METHOD FOR INTERLEAVED STORAGE OF DATA ELEMENTS |
摘要 |
A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits. |
申请公布号 |
US2015121019(A1) |
申请公布日期 |
2015.04.30 |
申请号 |
US201314063161 |
申请日期 |
2013.10.25 |
申请人 |
Arm Limited |
发明人 |
DASIKA Ganesh Suryanarayan;HOLM Rune;HILL Stephen John |
分类号 |
G06F12/06 |
主分类号 |
G06F12/06 |
代理机构 |
|
代理人 |
|
主权项 |
1. A data processing device comprising:
a plurality of storage circuits configured to store a plurality of data elements of b bits in an interleaved manner; and a consumer comprising a plurality of lanes, configured to be able to individually access each of said plurality of storage circuits, to receive into said plurality of lanes either a subset of said plurality of data elements or y bits of each of said plurality of data elements, and to execute a common instruction on each of said plurality of lanes, wherein b is greater than y and is an integer multiple of y; wherein each of said plurality of storage circuits is configured to store at most y bits of each of said data elements; wherein each of said plurality of storage circuits is configured to store at most y/b of said plurality of data elements; and wherein said plurality of storage circuits comprise no more than b/y storage circuits. |
地址 |
Cambridge GB |