发明名称 |
DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS |
摘要 |
A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region. |
申请公布号 |
WO2015061414(A1) |
申请公布日期 |
2015.04.30 |
申请号 |
WO2014US61719 |
申请日期 |
2014.10.22 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF MICHIGAN |
发明人 |
WENTZLOFF, DAVID D.;FAISAL, MUHAMMAD |
分类号 |
H03L7/07;H03L7/16 |
主分类号 |
H03L7/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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