发明名称 集積回路
摘要 There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by "K" and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.
申请公布号 JP5710425(B2) 申请公布日期 2015.04.30
申请号 JP20110185229 申请日期 2011.08.26
申请人 株式会社東芝 发明人 大 國 英 徳;崔 明 秀
分类号 H03L7/08;H03K5/00;H03K5/1252;H03K5/26 主分类号 H03L7/08
代理机构 代理人
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