发明名称 SYSTEM, METHOD, AND APPARATUS FOR PERFORMING CACHE FLUSH OF PAGES OF GIVEN RANGE AND TLB INVALIDATION OF ENTRIES OF GIVEN RANGE
摘要 PROBLEM TO BE SOLVED: To provide a system, a method, and an apparatus for performing flushing of a plurality of cache lines and/or invalidation of a plurality of translation look-aside buffer (TLB) entries.SOLUTION: In a method, in order to flush a plurality of cache lines of a processor, the plurality of cache lines of the processor are flushed, according to a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed.
申请公布号 JP2015084250(A) 申请公布日期 2015.04.30
申请号 JP20150000202 申请日期 2015.01.05
申请人 INTEL CORP 发明人 DIXON MARTIN G;SCOTT D RODGERS
分类号 G06F12/08;G06F12/10 主分类号 G06F12/08
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