| 摘要 |
A reception circuit includes: an equalizer; a comparator to compare an output signal of the equalizer with first, second, and third thresholds at a first-timing to output first, second, and third comparison-results, respectively; a selector to select any one of the first and second comparison-results based on a determination-result at a timing before the first-timing, and update the determination-result; a detector to detect a phase information based on the first or second comparison-result not selected; a shifter to adjust a sampling clock phase based on the phase information detected; and a controller to set a third threshold based on the first and second thresholds by either adjusting the first and second thresholds based on the output signal amplitude or adding/subtracting a first value to/from the output signal, detect an equalization-result based on the third comparison-result by the set third threshold, and adjust an equalization coefficient based on the detected equalization-result. |
| 主权项 |
1. A reception circuit to reproduce a data signal based on a data determination result of determining an amplitude level of an input data signal at a sampling timing synchronized with a sampling clock, the reception circuit comprising:
an equalizer configured to perform an equalization process on the input data signal; a comparator configured to compare an output data signal of the equalizer with a first threshold value, a second threshold value, and a third threshold value at a first sampling timing to output a first comparison result, a second comparison result, and a third comparison result, respectively; a selector configured to select any one of the first comparison result and the second comparison result based on the data determination result at a second sampling timing before the first sampling timing, and update the data determination result; a phase detector configured to detect phase information based on the first comparison result or the second comparison result which is not selected by the selector; a phase shifter configured to adjust a phase of the sampling clock based on the phase information detected by the phase detector; and a controller configured to set a third threshold value based on the first threshold value and the second threshold value by either adjusting the first threshold value and the second threshold value based on the amplitude of the output data signal or adding or subtracting a first value to or from the output data signal, detect an equalization result at the equalizer based on the third comparison result by the set third threshold value, and adjust an equalization coefficient of the equalizer based on the detected equalization result. |
