APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS

摘要

Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

主权项

1. A latch comprising:
a first AND-OR-invert (AOI) logic gate having an input to receive an input data value; and a second AOI logic gate having an input to receive a logical opposite of the data value; the second AOI logic gate coupled to the first AOI logic gate such that an output of the first AOI logic gate is coupled to another input of the second AOI logic gate and an output of the second AOI logic gate is coupled to another input of the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node.