METHOD OF MANUFACTURING HIGH RESISTIVITY SOI WAFERS WITH CHARGE TRAPPING LAYERS BASED ON TERMINATED SI DEPOSITION

摘要

A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.

主权项

1. A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon on insulator device, the single crystal semiconductor handle wafer comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle wafer and the other of which is a back surface of the single crystal semiconductor handle wafer, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle wafer, a bulk single crystal semiconductor region, and the central plane of the single crystal semiconductor handle wafer between the front and back surfaces of the single crystal semiconductor handle wafer, wherein the single crystal semiconductor handle wafer has a minimum bulk resistivity of at least 100 Ohm-cm, the method comprising:
forming a first semiconductor layer on the front surface layer of the single crystal semiconductor handle wafer, wherein the first semiconductor layer has a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge; passivating the first semiconductor layer; and forming a second semiconductor layer on the passivated first semiconductor layer, wherein the second semiconductor layer has a polycrystalline or an amorphous structure and comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge.