TECHNIQUE FOR FABRICATION OF MICROELECTRONIC CAPACITORS AND RESISTORS

摘要

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

主权项

1. An integrated electronic structure comprising:
a semiconductor substrate extending in a first plane; a pair of metal serpentines in a vertical orientation orthogonal to the first plane of the substrate; and a dielectric separating the pair of metal serpentines, the integrated electronic structure forming:
a vertical serpentine resistor;a plurality of horizontal parallel plate capacitors; anda plurality of generally vertical parallel plate capacitors.