TRACING MECHANISM FOR RECORDING SHARED MEMORY INTERLEAVINGS ON MULTI-CORE PROCESSORS

摘要

A memory race recorder (MRR) is provided. The MRR includes a multi-core processor having a relaxed memory consistency model, an extension to the multi-core processor, the extension to store chunks, the chunk having a chunk size (CS) and an instruction count (IC), and a plurality of cores to execute instructions. The plurality of cores executes load/store instructions to/from a store buffer (STB) and a simulated memory to store the value when the value is not in the STB. The oldest value in the STB is transferred to the simulated memory when the IC is equal to zero and the CS is greater than zero. The MRR logs a trace entry comprising the CS, the IC, and a global timestamp, the global timestamp proving a total order across all logged chunks.

主权项

1. A multi-core processor comprising:
a memory to store a chunk, the chunk having a chunk size (CS) and an instruction count (IC), the chunk comprising instructions; an allocated memory to store a memory race recorder (MRR) trace, the MRR trace comprising the CS, the IC and a global timestamp of each chunk, the MRR trace logged by a MRR; a plurality of cores to execute instructions within the chunks according to an execution order reconstructed from the MRR trace, the plurality of cores comprising:
a plurality of registers to store data for use in execution of load instructions and store instructions;a store buffer (STB) to store a value for the store instructions; anda simulated memory to store the value when the value is not in the STB.