发明名称 |
SEMICONDUCTOR PACKAGE |
摘要 |
A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6. |
申请公布号 |
US2015115429(A1) |
申请公布日期 |
2015.04.30 |
申请号 |
US201414585575 |
申请日期 |
2014.12.30 |
申请人 |
MediaTek Inc. |
发明人 |
CHEN Tai-Yu;LEE Chung-Fa;HSU Wen-Sung;LIN Shih-Chin |
分类号 |
H01L23/373;H01L23/00;H01L23/367;H01L23/498;H01L23/29;H01L23/31 |
主分类号 |
H01L23/373 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor package, comprising:
a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6. |
地址 |
Hsin-Chu TW |