MULTI-PROTOCOL I/O INTERCONNECT TIME SYNCHRONIZATION

摘要

Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for synchronizing time across the multi-protocol I/O interconnect may include providing a first local time of a first switch of a switching fabric of a multi-protocol interconnect to a second switch of the switching fabric, and adjusting a second local time of the second switch to the first local time. Other embodiments may be described and claimed.

主权项

1. An integrated circuit device comprising:
a switch, a local clock wherein the local clock is a free-running oscillator, and at least one port, wherein the integrated circuit device is a first integrated circuit device and is to:
send a first time synchronization message to a second integrated circuit device at a first local time of the first integrated circuit device;receive by a first port of the at least one port a second time synchronization message from the second integrated circuit device wherein the second time synchronization message comprises an ordered data set comprising a time stamp point,generate a time stamp when the time stamp point of the second time synchronization message passes a reference point in the first integrated circuit device wherein the time stamp is at a second local time of the first integrated circuit device,receive a third time synchronization message comprising a third and a fourth local time of the second integrated circuit device wherein the third time synchronization message is received at a different time than the second time synchronization message,determine a first offset value of local time of the first integrated circuit device from local time of the second integrated circuit device wherein determining includes calculating the first offset value based at least in part on the time stamp generated in the first integrated circuit device and the first local time of the first integrated circuit device, and the third and fourth local times of the second integrated circuit device and on time asymmetry corrections between transmit and receive paths between the first integrated circuit device and the second integrated circuit device, wherein the time asymmetry corrections correct for asymmetry between the transmit and receive paths between the first integrated circuit device and the second integrated circuit device.