| 发明名称 |
METHOD, APPARATUS AND SYSTEM FOR DYNAMICALLY CONTROLLING AN ADDRESSING MODE FOR A CACHE MEMORY |
| 摘要 |
In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed. |
| 申请公布号 |
US2015120998(A1) |
申请公布日期 |
2015.04.30 |
| 申请号 |
US201314126921 |
申请日期 |
2013.10.31 |
| 申请人 |
Wang Kebing;Bian Zhaojuan;Zhou Wei;Wang Zhihong |
发明人 |
Wang Kebing;Bian Zhaojuan;Zhou Wei;Wang Zhihong |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first portion of a cache memory associated with a first core, the first cache memory portion of a distributed cache memory, wherein the first cache memory portion is dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores including the first core, according to an addressing mode. |
| 地址 |
Shanghai CN |
