Radio Frequency (RF) Receivers With Whitened Digital Clocks And Related Methods

摘要

Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.

主权项

1. A receiver system having whitened digital processing, comprising:
a radio frequency (RF) front-end configured to receive RF input signals and to output analog signals associated with a channel within the RF input signals; digital receive path circuitry configured to receive the analog signals, to convert the analog signals into digital information, to process the digital information, and to output digital data associated with the channel, the digital receive path circuitry comprising:
a whitened clock generator configured to generate a whitened clock having random variations, the whitened clock generator comprising:
a randomizer configured to provide random values; anda clock generator configured to receive the random values and to output the whitened clock, the clock generating comprising a nominal clock control block configured to generate nominal control parameters, a combiner configured to combine the nominal control parameters with the random values to generate whitened control parameters, and a digital clock generator configured to output the whitened clock based upon the whitened control parameters; anda digital processing block configured to operate based upon the whitened clock; wherein the RF front-end and the digital receive path circuitry are integrated within a single integrated circuit.