发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.
申请公布号 US2015116018(A1) 申请公布日期 2015.04.30
申请号 US201414320168 申请日期 2014.06.30
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHEN Huan-Neng;YEN Kuang-Kai;KUO Feng-Wei;LIAO Hsien-Yuan;LEE Tsung-Hsiung;JOU Chewn-Pu;STASZEWSKI Robert Bogdan
分类号 H03L7/091;H03L7/099;H03L7/093 主分类号 H03L7/091
代理机构 代理人
主权项 1. A circuit, comprising: a digitally-controlled oscillator (DCO) configured for generating an oscillator output signal; a controller configured for setting an oscillation frequency of the oscillator output signal in accordance with a fractional phase part; a divider configured for converting the oscillator output signal into N-phased oscillator output signals corresponding to one oscillation period of the digitally-controlled oscillator; and a phase converter module, comprising: a period extender, configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator;a phase finder comprising M*N stages of logic circuits connected in parallel, each stage of the logic circuits configured for sampling the oscillator output signal with one of the M*N-phased oscillator output signals for calculating an estimated value of the fractional phase part; anda time-to-digital converter configured for sampling one of the N-phased oscillator output signals with a reference-frequency signal to calculate a precise value of the fractional phase part.
地址 Hsinchu TW