| 摘要 |
Provided is a small-area semiconductor device in which a decoder circuit for selecting a memory is configured using Surrounding Gate Transistors (SGTs) each being a vertical transistor. Provided is a semiconductor device wherein in a decoder circuit configured using a plurality of MOS transistors arranged in m rows and n columns, the MOS transistor constituting the decoder circuit is formed on a planar silicon layer formed on a substrate, has a drain, a gate, and a source which are disposed in a vertical direction, and has a structure in which the gate surrounds a silicon pillar, the planar silicon layer is composed of a first activation region having a first conductivity type, and a second activation region having a second conductivity type, and both the regions are connected via a silicon layer formed on the surface of the planar silicon layer, thereby configuring the small-area decoder circuit. |
