PROTOCOL CHECKING LOGIC CIRCUIT FOR MEMORY SYSTEM RELIABILITY

摘要

A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

主权项

1. A computing system, the system comprising:
a buffer integrated circuit device comprising: a substrate member comprising a silicon bearing material; an output driver formed on the substrate member, the output driver having at least a command bus and an address bus, the command bus and the address bus being configured to a plurality of memory devices; a protocol and parity checking block (“Block”), the protocol and parity checking block comprising a protocol circuit formed on the silicon bearing material and a parity circuit configured with the protocol circuit; a table configured in the block, the table being programmable with a plurality of timing parameters, the plurality of timing parameters being at least one or two of tCL, tRCD, tRP, tWR, tAL, tRFC, tRRD, tCCD, tRAS, or tCWL; a memory state block, the memory state block coupled to the table; and a command history table, the command history table coupled to the table, and configured with the memory state block to process protocol information for all commands that pass through the Block; and a host memory controller in communication with the buffer integrated circuit device.