pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains

摘要

A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

主权项

1. An embedded memory test system comprising:
a programmable Built In Self Test (pBIST) engine; a plurality of sub chips performing memory testing and data logging functions; and a plurality of asynchronous bridges connecting the pBIST engine to said sub chips, each of said plurality of asynchronous bridges operable to voltage level shift the pBIST output signals to match a voltage domain of an applicable sub chip, each of said plurality of asynchronous bridges including
a plurality of voltage level shifters;a plurality of pointer registers operable to increment on each cycle as indicated by a data valid signal;a plurality of synchronization registers; anda plurality of data buffer register banks.