Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread

摘要

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

主权项

1. A circuit arrangement, comprising:
a plurality of hardware threads disposed in a plurality of processing cores, each processing core including a register file and at least one hardware thread among the plurality of hardware threads, the register file in each processing core including a plurality of local registers; and a variable transfer network coupled between the plurality of processing cores, the variable transfer network configured to communicate a variable between a source hardware thread in a source processing core among the plurality of processing cores and a destination hardware thread in a destination processing core among the plurality of processing cores; and a plurality of variable registers, each variable register allocated to an individual hardware thread among the plurality of hardware threads, wherein the variable transfer network is configured to communicate the variable to a variable register allocated to the source hardware thread in the destination processing core in response to the source hardware thread in the source processing core writing to the variable register allocated to the destination hardware thread in the source processing core.