发明名称 Strained transistor structure
摘要 A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.
申请公布号 US9018051(B2) 申请公布日期 2015.04.28
申请号 US201414164055 申请日期 2014.01.24
申请人 STMicroelectronics, Inc. 发明人 Dove Barry
分类号 H01L21/335;H01L29/66;H01L21/28;H01L23/522;H01L29/423;H01L29/78 主分类号 H01L21/335
代理机构 Seed IP Law Group PLLC 代理人 Seed IP Law Group PLLC
主权项 1. A method comprising: forming a gate dielectric on a substrate; forming a trapezoidal gate electrode having a lower surface abutting the gate dielectric, an upper surface, and sloped sidewalls, the upper surface being narrower than the lower surface; using the trapezoidal gate electrode as a mask, implanting dopant ions into the substrate to form source and drain regions; and forming a strain-inducing layer overlying the trapezoidal gate electrode and the source and drain regions, the strain-inducing layer configured to induce strain in a channel region, wherein the trapezoidal gate includes a rectangular extension for use as a contact landing pad, and further comprising forming a metal contact to the trapezoidal gate, the metal contact intersecting the contact landing pad.
地址 Coppell TX US