发明名称 Gate driver for enhancement-mode and depletion-mode wide bandgap semiconductor JFETs
摘要 A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
申请公布号 US9019001(B2) 申请公布日期 2015.04.28
申请号 US201213468287 申请日期 2012.05.10
申请人 Power Integrations, Inc. 发明人 Kelley Robin Lynn;Rees Fenton
分类号 H03K17/687;H03K17/0412 主分类号 H03K17/687
代理机构 代理人
主权项 1. A two-stage gate driver circuit for driving a junction field effect transistor having a gate, a source, and a drain, the two-stage gate driver circuit comprising: an input for receiving an input control pulse signal with which switching of the junction field effect transistor is to be synchronized; a first on circuit that provides, in response to the input control pulse signal, a forward gate current to the junction field effect transistor at least during a conduction stage of the junction field effect transistor; a second turn-on circuit that provides, in response to the input control pulse signal, a current to charge the gate during at least part of a turn-on stage of the junction field effect transistor, wherein the current to charge the gate is relatively higher than the forward gate current; and a pull-down circuit, wherein the first on circuit, the second turn-on circuit and the pull-down circuit are electrically coupled between the input and the gate of the junction field effect transistor in parallel, and wherein the current to charge the gate during at least part of a turn-on stage of the junction field effect transistor is a pulse that terminates while the forward gate current is provided by the first on circuit.
地址 San Jose CA US