| 发明名称 |
Circuit arrangement and method for low power mode management with delayable request |
| 摘要 |
For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value. |
| 申请公布号 |
US9021287(B2) |
申请公布日期 |
2015.04.28 |
| 申请号 |
US201213602394 |
申请日期 |
2012.09.04 |
| 申请人 |
Intel Mobile Communications GmbH |
发明人 |
Hildebrand Uwe;Esswein Matthias;Nothdurft Thomas;Macher Stefan;Kliemann Uwe |
| 分类号 |
G06F1/00;G06F1/32;H04W52/02 |
主分类号 |
G06F1/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit arrangement comprising:
a clock generator configured to generate a clock signal; a circuit having a low power mode; and a controller, configured to
receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode;check whether the request is delayable upon reception of the request; andtrigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value if it has been detected that the request is delayable. |
| 地址 |
Neubiberg DE |
