Systems and methods involving phase detection with adaptive locking/detection features

摘要

Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

主权项

1. A method for detecting and adaptively locking phase of circuitry, the method comprising:
detecting an input signal phase of a reference clock and an output signal phase of a feedback clock; adjusting, via a digital adjustment mode, the feedback clock until the output signal phase is approximately equal to the input signal phase; when the output signal phase is approximately equal to the input signal phase, entering an analog adjustment mode; adjusting the output signal until the output signal phase is equal to the input signal phase, whereupon the circuitry changes from an unlocked state to a locked state; wherein the analog adjustment mode is continued after the locked state is reached and includes utilization of a widened phase detection window, which enables ability to hold the circuitry in the locked state when the circuitry is experiencing jitter or noise, thereby reducing spurious transition back to the unlocked state.