| 发明名称 | Duty cycle correction circuit and operation method thereof | ||
| 摘要 | A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal. | ||
| 申请公布号 | US9018994(B2) | 申请公布日期 | 2015.04.28 |
| 申请号 | US201313844928 | 申请日期 | 2013.03.16 |
| 申请人 | SK Hynix Inc. | 发明人 | Kang Shin-Deok;Jang Jae-Min;Kim Yong-Ju;Choi Hae-Rang |
| 分类号 | H03K5/04;H03K5/156 | 主分类号 | H03K5/04 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A duty cycle correction circuit, comprising: a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal; a tracking type setting unit configured to generate a tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal; and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal, wherein the first tracking type comprises a successive approximation register (SAR) tracking type, and the second tracking type comprises a linear tracking type. | ||
| 地址 | Gyeonggi-do KR | ||