Duty cycle tuning circuit and method thereof

摘要

A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock.

主权项

1. A duty cycle tuning circuit, comprising:
a plurality of interpolation circuits, each for receiving a plurality of phase clocks of a multiphase clock signal, and interpolating an interpolation clock from two phase clocks with adjacent phases of the phase clocks of the multiphase clock signal, wherein the phase clocks have the same frequency but different phases; an edge detection circuit, for generating an output clock according to an edge of the interpolation clocks, a rising edge of the output clock corresponding to an edge of one of the interpolation clocks, and a falling edge of the output clock corresponding to an edge of another one of the interpolation clocks; and a delay chain, connected electrically to the edge detection circuit.