发明名称 System for accessing a register file using an address retrieved from the register file
摘要 A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.
申请公布号 US9021238(B2) 申请公布日期 2015.04.28
申请号 US201213372103 申请日期 2012.02.13
申请人 International Business Machines Corporation 发明人 Chang Xiao Tao;Liu Qiang
分类号 G06F7/38;G06F9/00;G06F9/44;G06F15/00;G06F9/35;G06F9/30;G06F9/38 主分类号 G06F7/38
代理机构 Suiter Swantz pc llo 代理人 Suiter Swantz pc llo
主权项 1. A data processing method based on pipeline, comprising the following steps: fetching an instruction at an instruction-fetch stage, and inputting a specific instruction into a decode stage, wherein said specific instruction indicating whether contents of a register in a specific register file are to be utilized as an index; at the decode stage, accessing contents of the register in the specific register file, utilizing the contents as said index for accessing the specific register file, and accessing the specific register file based on said index; and at an execution stage, receiving an access result of said decode stage, and implementing computations according to the access result of the decode stage, wherein said specific register file includes multiple general-purpose registers and said accessing the specific register file further comprises: providing access to said multiple general-purpose registers using a first multiplexor;providing access to said multiple general-purpose registers using a second multiplexor; andproviding an output of said first multiplexor as a control input to said second multiplexor and as an input to a third multiplexor, wherein: the output of said first multiplexor and the output of said second multiplexor are provided to the third multiplexor simultaneously for selection; when said specific instruction does not indicate the contents of the register in the specific register file are to be utilized as the index, the third multiplexor selects to output to the execution stage the output of said first multiplexor; and when said specific instruction indicates the contents of the register in the specific register file are to be utilized as the index, the third multiplexor selects to output to the execution stage the output of said second multiplexor.
地址 Armonk NY US
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