| 发明名称 |
System and method for improving ECC enabled memory timing |
| 摘要 |
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves. |
| 申请公布号 |
US9021170(B2) |
申请公布日期 |
2015.04.28 |
| 申请号 |
US201213531002 |
申请日期 |
2012.06.22 |
| 申请人 |
Texas Instruments Incorporated |
发明人 |
Langadi Saya Goud |
| 分类号 |
G06F13/00;G06F11/10;G06F13/364 |
主分类号 |
G06F13/00 |
| 代理机构 |
|
代理人 |
Pessetto John R.;Cimino Frank D. |
| 主权项 |
1. A pipeline communication system comprising:
a master and a plurality of slaves configured to communicate with each other, each of the plurality of slaves comprising a memory, and being configured to generate a first ready signal and a second ready signal, wherein the first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves, wherein the second ready signal is generated independent of an error check in each of the plurality of slaves; wherein each of the plurality of slaves generates an abort signal in response to a state when the first ready signal and the second ready signal are not in a same logic state, wherein the abort signal is provided back to the plurality of slaves and wherein each of the plurality of slaves aborts the operation in response to the abort signal. |
| 地址 |
Dallas TX US |
