PWM signal output circuit

摘要

A PWM-signal-output circuit includes a detecting unit to detect time periods during which a speed signal with logic level changing alternately and having a period corresponding to a motor-rotation speed is at one and the other logic levels; a generating unit configured to, when the logic level of the speed signal changes, generate a signal to increase and thereafter decrease a current flowing through a motor coil within a first time period detected by the detecting unit, in a second time period occurring after the first time period; and a second generating unit configured to, when the first time period has elapsed after a change in the logic level of the speed signal but before a subsequent change in the logic level thereof in the second time period, generate the signal from when the first time period has elapsed until when the logic level thereof changes.

主权项

1. A PWM signal output circuit configured to output a PWM signal to a drive circuit configured to drive a motor based on the PWM signal, the PWM signal output circuit comprising:
a detecting circuit configured to detect a first speed time period during which a speed signal is at one logic level and a second speed time period during which the speed signal is at another logic level, based on the speed signal whose logic level changes in an alternate manner, the speed signal having a period corresponding to a rotation speed of the motor; a first generating circuit configured to, in response to the logic level of the speed signal changing, generate the PWM signal to increase and thereafter decrease current flowing through a motor coil of the motor within a first PWM time period wherein the PWM signal is generated according to a duration of the first speed time period which is detected by the detecting circuit in the second speed time period during which the speed signal is at the another logic level, the second speed time period and the first PWM time period occurring after the first speed time period; and a second generating circuit configured to, in response to the first PWM time period elapsing after the change in the logic level of the speed signal but before a subsequent change in the logic level of the speed signal in the second speed time period, generate the PWM signal with a predetermined duty cycle from substantially when the first PWM time period has elapsed until substantially the subsequent change in the logic level of the speed signal.