Memory management unit tag memory

摘要

A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

主权项

1. A method for generating a speculative miss signal from first and second operands without requiring addition of the first and second operands, comprising:
receiving a first operand comprising base address bits and a second operand comprising offset address bits; pairing each of the base address bits with a corresponding bit from the offset address bits, thereby generating a plurality of paired bits; generating a plurality of logical values for each of the plurality of paired bits; generating a carry-out value from at least a most significant indexing bit of the base address bits and the most significant indexing bit of the offset address bits; and using the plurality of logical values and the carry-out value to access the indexed content addressable memory (CAM) array to generate two speculative miss signals by applying PGZ values to CAM bitcells in even and odd arrays, where each CAM bitcell comprises embedded partial A+B=K comparison logic circuitry for generating required carry-in and produced carry-out values for each CAM bitcell; and selecting one of the two speculative miss signals for output based on a sum value computed by adding at least the least significant bit of the base address bits with the least significant bit of the offset address bits; where applying PGZ values to each CAM bitcell comprises:
applying a Zero (Z) value, a complementary Generate ( G) value, and a first data node in the CAM bitcell to a first logic circuit to generate a complementary carry-out value ( Cout);applying a Generate (G) value, Propagate (P) value and a second data node in the CAM bitcell to a second logic circuit to generate a carry-out value (Cont);applying a Propagate (P) value, complementary Propagate ( P) value, a first data node in the CAM bitcell, and a second data node in the CAM bitcell to a third logic circuit to generate a carry-in value (Cin); andapplying a Propagate (P) value, complementary Propagate ( P) value, a first data node in the CAM bitcell, and a second data node in the CAM bitcell to a fourth logic circuit to generate a complementary carry-in value ( Cin).