发明名称 Solid-state imaging device, imaging system, and method for driving solid-state imaging device
摘要 In a solid-state imaging device which includes column analog-to-digital conversion circuits (ADCs) for converting pixel signals output from pixels into digital signals, each of the column ADCs includes a comparator which outputs a result of voltage comparison (comparison result signal) between the voltage of the pixel signal and an analog ramp voltage; a column counter which counts a column counter clock signal, which is either a clock signal or a phase-shifted clock signal, and stores a value represented by upper bits of a count value at a time of change in the comparison result signal; and a first latch unit which stores a value represented by lower bits of the count value. A second latch unit stores the value stored in the first latch unit.
申请公布号 US9019142(B2) 申请公布日期 2015.04.28
申请号 US201213665327 申请日期 2012.10.31
申请人 Panasonic Intellectual Property Management Co., Ltd. 发明人 Hiraoka Toshiaki;Shimomura Kenichi;Abe Yutaka;Shimizu Yusuke
分类号 H03M1/56;H04N5/335;H04N5/374;H04N5/378;H03M1/14;H03M1/12 主分类号 H03M1/56
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A solid-state imaging device which includes a plurality of sensing elements arranged in a matrix format for measuring physical quantities, and a plurality of column analog-to-digital conversion circuits (ADCs) for converting signals output from the sensing elements into digital signals, each of the column ADCs comprising: a comparator configured to output a comparison result signal which indicates a result of voltage comparison between a voltage of a signal output from the sensing elements and an analog ramp voltage generated from a reference clock signal; a column counter configured to count a column counter clock signal, which is either the reference clock signal or a phase-shifted reference clock signal, and to store a value represented by upper bits of a count value at a time of change in the comparison result signal; a first latch unit configured to store a latch clock signal which represents a value represented by lower bits of the count value; and a second latch unit configured to store a value corresponding to the value stored in the first latch unit.
地址 Osaka JP