Accumulator-type fractional N-PLL synthesizer and control method thereof

摘要

There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

主权项

1. An accumulator-type fractional N-PLL synthesizer comprising:
a voltage-controlled oscillator (VCO); a fractional frequency divider, disposed in a feedback path of an output signal of the VCO, for generating a frequency divider output signal of a fractional frequency division number; an accumulator for supplying an overflow signal for periodically switching a frequency division number of the fractional frequency division number, to the fractional frequency divider; and a phase detector for detecting a phase difference between the frequency divider output signal and a predetermined reference signal to generate a control input signal to the VCO based on the detected phase difference, wherein the accumulator generates an error signal having fractional phase error information, wherein the phase detector receives the error signal and the output signal of the VCO, and corrects the phase difference between the frequency divider output signal and the reference signal, using the error signal and the output signal of the VCO, and wherein the phase detector includes:
a fractional phase error pulse generation circuit for generating a phase error pulse signal having a pulse width proportional to a fractional phase error and generating a feedback signal, based on the frequency divider output signal and the error signal,a frequency and phase detector for generating a frequency and phase detection output signal having a pulse width proportional to a difference in frequency and phase between the reference signal and the feedback signal, anda fractional phase error removal circuit for generating an UP signal and a DN signal with the fractional phase error included in the frequency and phase detection output signal being reduced, based on the phase error pulse signal.