| 摘要 |
<p>Successive Approximation Register Analog To Digital Converter Circuit And Conversion Method Thereof. A successive approximation ADC is provided. This invention addresses the problems of parasitic effects and conversion time issues associated with passive charge redistribution SAR ADCs. Dual capacitor arrays with plurality of capacitors and switches, with equal capacitance including parasitic at every capacitor is employed. In addition capacitor arrays perform more than one operation simultaneously, that include passive charge sharing, charging and discharging. These features make the SAR ADC to have lower power consumption, surface area and conversion time amongst passive charge redistribution SAR ADCs.</p> |
