STACKED DIE PACKAGE

摘要

Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.

主权项

1. An integrated circuit package, comprising:
a first integrated circuit die having a first integrated circuit layout; and, a second integrated circuit die having a second integrated circuit layout, the second integrated circuit layout including a plurality of active through-silicon vias and a plurality of passive through-silicon vias, the first integrated circuit stacked on the second integrated circuit to align a plurality of active through-silicon vias on said first integrated circuit with a corresponding plurality of passive through-silicon vias on said second integrated circuit.