RESISTIVE MEMORY DEVICE, OPERATING METHOD THEREOF, AND SYSTEM HAVING THE SAME

摘要

A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.

主权项

1. A resistive memory device comprising:
a memory cell array comprising a plurality of resistive memory cells; an address decoder suitable for decoding an address signal and selecting the resistive memory cells; a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array; a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder; and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data, wherein in the write operation, after the plurality of write data are sequentially programmed in respective resistive memory cells, whether the programmed resistive memory cells are in target resistance levels is verified sequentially.