Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film

摘要

A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.

主权项

1. A three-dimensional semiconductor device, comprising:
a substrate; a first functional element extending vertically from the substrate; a plurality of second functional elements disposed at intervals along the first functional element; and a plurality of charge trap layers, each disposed between the first functional element and a corresponding second functional element, wherein each of the charge trap layers is separate and discrete from the other charge trap layers.