| 发明名称 |
IMPLEMENTING MISR COMPRESSION METHODS FOR TEST TIME REDUCTION |
| 摘要 |
A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR. |
| 申请公布号 |
US2015113348(A1) |
申请公布日期 |
2015.04.23 |
| 申请号 |
US201314060744 |
申请日期 |
2013.10.23 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Douskey Steven M.;Kusko Mary P.;Lichtenau Cédric |
| 分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for implementing multiple input signature register (MISR) compression for test time reduction, said method comprising:
providing a first MISR, providing a second MISR provided with the first MISR, and providing a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR. |
| 地址 |
Armonk NY US |
