发明名称 DOT INVERSION CONFIGURATION
摘要 This disclosure provides systems, methods and apparatus for an arrangement of pixels and interconnects in a display. In one aspect, polarities of pixels may be in a dot inversion configuration, or checkerboard pattern, to reduce the visibility of flicker. Various interconnect alternatively couple between modules in different columns or rows to provide dot inversion.
申请公布号 US2015109265(A1) 申请公布日期 2015.04.23
申请号 US201314059320 申请日期 2013.10.21
申请人 QUALCOMM MEMS Technologies, Inc. 发明人 Chan Edward Keat Leem;Wen Bing;Kim Cheonhong;Van Lier Wilhelmus Johannes Robertus;Ho Chih-Hsiang;He Rihui;Tung Ming-Hau;Govil Alok;Seo Jae Hyeong
分类号 G09G3/20 主分类号 G09G3/20
代理机构 代理人
主权项 1. A circuit including an array of display units, the circuit comprising: a first three-terminal display unit having a first terminal, and a second terminal, and a third terminal, the first terminal coupled to a first interconnect, the second terminal coupled to a second interconnect, and the third terminal coupled to a seventh interconnect; a second three-terminal display unit having a first terminal and, a second terminal, and a third terminal, the first terminal coupled to a third interconnect, the second terminal coupled to a fourth interconnect, and the third terminal coupled to the seventh interconnect; a third three-terminal display unit having a first terminal, and a second terminal, and a third terminal, the first terminal coupled to a fifth interconnect, the second terminal coupled to the fourth interconnect, and the third terminal coupled to the seventh interconnect; and a fourth three-terminal display unit having a first terminal, and a second terminal, and a third terminal, the first terminal coupled to the first interconnect, the second terminal coupled to a sixth interconnect, and the third terminal coupled to the seventh interconnect.
地址 San Diego CA US