DECODING METHOD, DECODING CIRCUIT, MEMORY STORAGE DEVICE AND CONTROLLING CIRCUIT UNIT

摘要

A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.

主权项

1. A decoding method for low density parity code, and for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of first memory cells, and the decoding method comprises:
reading a data bit of each of the first memory cells; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of the low density parity code, obtaining reliability message of each of the data bits according to the checks, and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding, and correcting the data bit according to the index of the error bit.