SRAM LAYOUTS

摘要

Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.

主权项

1. An article of manufacture, comprising a computer readable storage medium, having stored thereon in a non-transitory manner a computer readable definition of shapes for a lithographic mask set for defining features to be formed on an integrated circuit using the mask set, wherein the features define a static random access memory comprising an array of memory cells, each particular one of the cells comprising:
first and second pass-gate transistors each connected in the cell to perform a pass gate function; first and second P-channel pull-up transistors each connected in the cell to perform a pull-up function; and first and second N-channel pull-down transistors, each connected in the cell to perform a pull-down function, each of the transistors having a respective gate electrode and respective first and second current path terminal, wherein the gate electrode of a particular one of the transistors of first one of the functions does not share a layout track with the gate electrodes of any of the transistors of either of the other two functions.