| 主权项 |
1. Processing apparatus comprising:
a bus; a first processor connected to the bus and configured to perform read and write operations over the bus according to a bus protocol; a second processor arranged to execute multiple threads; an inter-thread interconnect comprising a system of channel terminals, each operable to be used by one of the threads to perform input and output operations over a channel comprising a logical connection with another channel terminal, including being operable to perform input and output operations over a channel with another of said channel terminals used by another of said threads; and an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side having an instance of at least one channel terminal, wherein the first processor is thereby operable to communicate with a designated one of said threads via: (i) the bus and (ii) a respective one of said channels between the channel terminal of the interface and a respective one of the channel terminals of the inter-thread interconnect used by the designated thread, the interface providing an association between read and write operations over the bus and input and output operations performed by the channel terminal of the interface. |
