POWER LEVEL TRANSFER CIRCUIT, GATE ELECTRODE DRIVE CIRCUIT AND DISPLAY DEVICE

摘要

A power level transfer circuit, gate electrode drive circuit and display device, the power level transfer circuit comprising a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5) and a sixth transistor (M6); source electrodes are respectively connected to a direct current power supply (VDD); gate electrodes are respectively connected to a bias voltage terminal (VBias); the drain electrodes of the third transistor (M3) and the fifth transistor (M5) are connected as a first output terminal (OUT1); the drain electrodes of the fourth transistor (M4) and the sixth transistor (M6) are connected as a second output terminal (OUT2); the gate electrodes of both a first transistor (M1) and a second transistor (M2) are connected to an input signal terminal (VIn), and the source electrodes of both the first transistor (M1) and the second transistor (M2) are connected to the drain electrode of a seventh transistor (M0); the drain electrode of the first transistor (M1) is connected to the first output terminal (OUT1), and the drain electrode of the second transistor (M2) is connected to the second output terminal (OUT2); and the source electrode of the seventh transistor (M0) is connected to the ground power (VSS) of the source electrode, and the gate electrode of the seventh transistor (M0) is connected to the bias voltage terminal (VBias). Common mode voltages between two output terminals of the power level transfer circuit and the ground power of the source electrode do not drop.