| 主权项 |
1. A memory device comprising:
a plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction crossing the first direction; and a plurality of memory cells each coupled to corresponding two of the word lines and corresponding two of the bit lines, wherein each of the memory cells includes a memory element and two select transistors, the memory element being configured to store information on the basis of changes in resistance, wherein one terminal of the memory element is coupled to one of the two bit lines corresponding to the memory cell, wherein the other terminal of the memory element is coupled to respective drains of the two select transistors, wherein respective sources of the two select transistors are coupled to the other of the two bit lines corresponding to the memory cell, wherein a gate of one of the two select transistors is coupled to one of the two word lines corresponding to the memory cell, wherein a gate of the other of the two select transistors is coupled to the other of the two word lines corresponding to the memory cell, and wherein one column is formed by repeatedly arranging the memory cell in the first direction, and wherein a memory cell array is formed by repeatedly arranging the column in the second direction. |
