发明名称 |
Electronic circuit having serial latch scan chains |
摘要 |
<p>Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. Also disclosed is a method of initialising the electronic circuit.</p> |
申请公布号 |
GB2519359(A) |
申请公布日期 |
2015.04.22 |
申请号 |
GB20130018518 |
申请日期 |
2013.10.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CEDRIC LICHTENAU;JENS KUENZER;TILMAN GLOEKLER;ANDREAS KOENIG |
分类号 |
G06F11/22;G01R31/28;G06F11/27;G11C29/12 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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